1. Field of the Invention
The present invention relates generally to electronic design automation (EDA) and, more specifically, to EDA software tools relating to the use of timing diagrams to represent the input or output of a static timing engine.
2. Description of the Related Art
Logic simulation engines are software tools that a circuit design engineer may use to simulate the operation of a circuit. The tool may include a component that parses a netlist file representing a schematic diagram of the circuit and uses the resulting information about the circuit as input data for the simulation engine. Alternatively, or in addition, the tool may include a component that parses a hardware description language, such as Verilog.TM. or VHDL. The parser also refers to models of the various circuit devices or components, and these models include data relevant to the operation of the component, such as minimum set-up times required between changes in one input signal relative to another, minimum hold times required for inputs to remain steady, and minimum and maximum output delay times for the device to respond to the changes in its inputs. The tool may output the results of the logic simulation in the form of waveforms displayed on the video screen for the circuit design engineer to evaluate. A waveform is a graphical or visual representation of the manner in which a signal in the circuit changes with time. In other words, a waveform may indicate the transitions between logic states and the times at which they occur, relative to some reference time or relative to other displayed waveforms. Certain tools not only can generate waveforms as output data from a simulation but also can accept waveforms as input data to a simulation.
A timing diagram includes, in addition to a waveform, relationships between state transitions of different signals. For example, a timing diagram may not only display a clock waveform, a data waveform, and an output waveform, but may also indicate a set-up time between a transition or edge of the clock waveform and a transition of the input data waveform to valid input data, a delay time between the clock edge transition and transition of the output data waveform to valid output data, and a hold time between between another transition or edge of the clock waveform and a transition of the input data waveform back to invalid or potentially invalid data. A timing diagram typically indicates these relationships with dimension lines, arrows or similar graphics.
A standard language referred to as Timing Diagram Markup Language (TDML) has recently been proposed for communicating and storing timing diagrams in electronic format. The proposed TDML standard is available from the TDML Working Group of the Silicon Integration Initiative (Si2) organization, which operates as Si2, Inc. based in Austin, Tex. The TDML project is part of Si2's Electronic Component Information Exchange (ECIX) project. TDML is based on the Standard Generalized Markup Language (SGML), ISO 8879:1986. The goal behind defining TDML as a standard language supported by an appropriate standards organization such as ISO is to allow electronic component manufacturers to make computer-readable technical information relating to their products available to users via the Internet or similar means. A circuit design engineer could thus remotely retrieve the TDML files describing the operation of components of a circuit he or she wishes to simulate, and provide the TDML files directly as inputs to the simulation engine. Currently, such information must be read from data books published by the manufacturer either in print or electronically and then manually converted into component models readable by the simulation engine.
While commercially available logic simulation tools commonly use waveforms as input and output data, few such tools currently use timing diagrams. Logic simulation tools that provide output data in the form of timing diagrams are sometimes referred to as timing diagram tools. Their simulation engines operate by performing computations on data arrays or matrix-like data structures that represent a model of the circuit under simulation. The contents of the data structure is typically displayed in a spreadsheet-like manner in a window, while the timing diagrams are displayed in another window.
Another type of simulation engine that is widely used in commercially available EDA tools is sometimes referred to as a static timing engine. A static timing engine operates by performing computations on directed graph data structures using algorithms grounded in graph mathematics. In one common form of this data structure, the nodes of the graph represent nodes of the circuit at which the signals exist. The connections between the nodes (often referred to as arcs or segments, particularly in the context of a visual representation of a graph) represent the physical connections between the circuit nodes. Associated with each connection or arc is information regarding the temporal relationship of events that occur at the circuit node referenced by each end of the arc. Typical relationships include delays, set-up time requirements, hold time requirements, and pulse-width requirements. Note that an arc may exist between a node and itself and include associated information regarding the temporal relationship between two events that occur at that circuit node.
Tools that use static timing engines typically produce output in the form of text reports. The report can be a list of all nodes in the circuit under simulation, the signal transitions that occurred at each node, the times at which they occurred relative to a starting or reference time, and relationships between the transitions of certain signals and the transitions of certain other signal. Circuit design engineers have been known to manually convert such timing graph text reports into timing diagrams.
It has been suggested in the art to convert a certain type of timing graph into a timing diagram, but in that type of timing graph the nodes represent events, i.e., signal transitions. They do not represent signal nodes in the actual circuit. One commercially available tool that automates such conversion is PEARL, produced by Cadence Design Systems, Inc. of San Jose, Calif.
It would be desirable to provide a software tool that converts the type of timing graph in which nodes represent actual circuit nodes into timing diagrams and vice versa. This object and others are satisfied by the present invention in the manner described below.